1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor devices including metal polycide processes and, more particularly, to the prevention of high resistance formations due to agglomeration and inversion in conductors and other integrated circuit structures formed at high integration density.
2. Description of the Prior Art
Current ultra-large scale integrated circuits (ULSI), particularly those embodied in complementary metal-oxide-semiconductor (CMOS) technology, use polysilicon transistor gate electrodes capped with a low-resistance metal silicide layer. Corresponding structures may be employed for control gates of non-volatile memory cells. This combination of layers is often referred to in the art as a polycide structure. This polycide structure provides low sheet resistance in order to increase circuit performance in reducing RC time constant signal propagation delays since the interconnect resistance often limits performance of the ULSI integrated circuit. The low sheet resistance of the polycide structure becomes more critical as cross-sectional dimensions are reduced with increases in integration density.
In the process used to form the polycide structure, a refractory metal silicide is deposited on unpatterned doped polysilicon. A dielectric is then deposited to cover and electrically insulate the silicide layer. The sequence of layers is patterned and then heated to crystallize the silicide to develop the low sheet resistance properties thereof. As is known in the art, source and drain regions of CMOS structures are then formed using spacers and ion implants followed by annealing to correct implantation damage and diffuse the source and drain regions to a desired position, dopant/impurity concentration and profile, generically referred to as "drive in". It is particularly necessary that the polycide structure achieve its low sheet resistance properties during the annealing process and retain its low resistance properties through other high temperature processes such as dielectric reflow anneals which are often performed at temperatures in excess of 850.degree. C.
Titanium silicide is frequently used as a gate conductor in ULSI and other integrated circuits since it has the lowest sheet resistance among the refractory metal silicides. However, titanium silicide is a polymorphic material having both high and low resistance phases. The low temperature phase (e.g. C49, generally formed as it is deposited) is of relatively high resistance and must be transformed into the low resistance phase (e.g. C54) by an annealing process at a temperature in excess of 700.degree. C. The phase transformation becomes more difficult at decreasing cross-sectional dimensions of the polycide structure as the grain size becomes comparable to the conductor width or thickness. For conductors smaller than 0.5 .mu.m or in the so-called half-micron and smaller regimes, temperatures in excess of 850.degree. C. are needed for full phase transformation. However, these elevated temperatures have been observed to cause degradation of the low resistance properties of such fine conductors, particularly in comparison with the sheet resistance which should be achieved.
For titanium silicide, this thermal instability and degradation of conductivity is principally due to silicon agglomeration as silicon diffuses into the silicide layer from the polysilicon layer adjacent (e.g. below) it. The diffused silicon precipitates, enlarging or forming silicon grains which become large enough to fill a significant portion of the cross-section of the silicide layer, if not the entire cross-section thereof. Since the silicon grains are of substantial resistivity, it can be appreciated that agglomerations of silicon can compromise both performance and/or manufacturing yield of the integrated circuit. (Reliability of "tested good" devices is not generally affected since high resistance on minimum dimension structures can be readily detected during testing of either the performance, such as maximum clock rate, or functionality of the device.)
A more severe form of degradation is referred to as polycide inversion, for which agglomeration may be considered a precursor phenomenon. Polycide inversion occurs during annealing processes at higher temperatures and/or for longer periods of time than the annealing processes in which agglomeration is observed. In polycide inversion, both silicon and titanium diffuse into their complementary layers (e.g. titanium into the doped polysilicon as well as silicon into the silicide) with the result that the silicon and silicide exchange layers in local, randomly distributed locations. The effects may be more severe since both layers are disrupted and, at some locations, titanium may penetrate the very thin gate oxide of transistors, causing device failure.
Thus, as integration density increases and conductor cross-sectional dimensions become correspondingly smaller, the temperature and/or duration of the anneal to produce a low resistance phase of the silicide must be increased, increasing the likelihood that agglomeration and, possibly, polycide inversion, will occur. Thus, the "process window" becomes smaller and process parameters become more critical as integration density increases.
While some processes are known which can increase the "process window" somewhat, none is fully successful for current or foreseeable feature size regimes and each presents additional problems which must be overcome. For example, thickening of the silicide layer increases cross-sectional area of the connection without increasing line width. However, the increased aspect ratio of the conductors thus produced introduces additional difficulty in reducing resolution of lithographic processes for gate etching and production of void-free gap filling. Therefore this expedient cannot be easily extended beyond the half-micron regime.
Rapid thermal anneal (RTA) processes which rapidly raise and lower wafer temperatures can increase the process window by reducing the time during which diffusion, and, hence, agglomeration and polycide inversion can occur. However, due to the increasing difficulty of producing a low resistance phase with decreasing cross-sectional dimensions of conductors, RTA is not generally sufficient for line widths in the half-micron regime. Reducing the thermal budget generally does not produce complete phase transformation and results in a trade-off between device performance (e.g. signal propagation speed) and manufacturing yield in small feature size regimes. Addition of phase transformation promoting agents such as metallics, as are disclosed in U.S. Pat. No. 5,510,295, entitled Method for Lowering the Phase Transformation Temperature of a Metal Silicide, may lower the process temperature but do not improve overall thermal stability unless subsequent process temperatures can be kept low and thus provide no effective increase in the process window.
Thus, it is seen that processes that provide for reliable manufacture of silicide structures at high yield as feature size is reduced beyond the half-micron regime have small or negligible process windows against silicon agglomeration and/or process inversion.